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The aim is to develop a very low-power interface IC for implantable pacemakers.

A very low-power CMOS mixed-signal IC for implantable pacemaker applications

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The aim is to develop a very low-power interface IC for implantable pacemakers.
Designed a single-chip mixed-signal IC integrating multiple functions.
Utilized subthreshold transistor designs and switched-capacitor circuit techniques.
Fabricated in a 0.5-/spl mu/m process with 200 k transistors housed in a 49 mm² area.
The IC operates at very low power consumption of 8 /spl mu/W.
Achieved nanopower circuit operations using innovative design techniques.

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Randomized trial demonstrates low power consumption in implantable devices, suggesting improved longevity and functionality.

Wong et al. (2004) studied this question.

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