This engineering study presents a power-optimized, fully integrated A/D interface for cardiac pacemakers capable of acquiring and digitizing atrial and ventricular electrical activity.
Facilitates miniaturized pacemaker electronics; leaves open clinical translation from this preclinical design.
This work presents an input stage for a cardiac pacemaker fully integrated in 0.35-/spl mu/m CMOS technology. The system can acquire and digitize to 8 bits both atrial and ventricular electrical activity. Log-domain circuits are exploited to amplify and filter the input signal, while /spl Sigma//spl Delta/ modulation is exploited to convert it. The design is power optimized, indeed the current consumption is limited to 2.9 /spl mu/A, while the power supply ranges from 2.8 to 1.8 V. The total area is 2.2 mm/sup 2/ and experimental data prove correct filtering and a total dynamic range of at least 47 dB.
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Gerosa et al. (2004) studied this question.
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