The development of a highly miniaturized, low-power wireless intra-cardiac acquisition chip demonstrates technical feasibility for advanced intra-cardiac monitoring systems.
May enable compact wireless cardiac monitors; leaves open clinical validation and integration.
This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 <tex-math notation="LaTeX">μ Vᵣₘₛ</tex-math> , and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 <tex-math notation="LaTeX">μ m</tex-math> standard CMOS technology and consumes 4.5 <tex-math notation="LaTeX">μ W</tex-math> while occupying 1.125 <tex-math notation="LaTeX">mm²</tex-math> .
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Rezaeiyan et al. (2023) studied this question.
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