A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications

This work presents an ultralow-power heart-rate system-on-a-chip (HR-SoC) for long-term continuous cardiac monitoring applications. A modified QRS-complex detection algorithm, verified on the MIT-BIH arrhythmia database, achieves a sensitivity (SE) of 99.99%, a positive predictive rate (PPR) of 99.68%, and an accuracy (ACC) of 99.68% while significantly reducing the power consumption compared to the conventional Pan-Tompkins algorithm. The system outputs averaged HRs (AHRs) and operates in an interrupt-driven architecture, dramatically saving memory resources and power consumption. The HR-SoC integrates an analog front end (AFE) for electrocardiograph (ECG) recording and a digital signal processing (DSP) back end for QRS detection, storage, and system scheduling and configuration. The AFE strikes a compromise among noise, linearity, and power consumption. Fabricated in 0.18- <tex-math notation="LaTeX">μ</tex-math> m CMOS technology, the HR-SoC features a compact area of 1.55 mm2. When operating at a 1-V power supply, it consumes only <tex-math notation="LaTeX">1.28~μ</tex-math> W in the AHR monitoring mode, with <tex-math notation="LaTeX">0.48~μ</tex-math> W consumed by the AFE and <tex-math notation="LaTeX">0.8~μ</tex-math> W by the DSP back end.