SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design

Deep spiking neural networks (SNNs) have gained significant attention in the current landscape of neural computing, primarily due to their remarkable energy efficiency and capability to perform complex computational tasks. This article presents the hardware implementation of a residual SNN (RSNN) architecture featuring four layers equipped with residual connections. We propose a novel edge-based data encoding scheme to enhance RSNN’s efficiency. This encoding scheme significantly accelerates the training and inference processes by5.2×and3.1×on an Nvidia A100 GPU having 80 GB of memory, compared to conventional encoding schemes, rate, latency, and delta encoding on the MNIST, fashion-MNIST (FMNIST), and KMNIST datasets. Moreover, it drastically reduces memory usage and energy consumption by~ \!37×and~ \!4.3×. In addition, this article proposes two distinct hardware implementations of the proposed RSNN using an AMD VCK190 field-programmable gate array (FPGA): sequential RSNN (SRSNN) and sequential–parallel RSNN (SPRSNN). SRSNN uses~ \!\!3×fewer hardware resources than SPRSNN on an FPGA. In contrast, SPRSNN exhibits10.6×and2×lower latency and power consumption than SRSNN. The proposed FPGA-based realizations show an accuracy of 98%, 89%, and 95% on the MNIST, FMNIST, and KMNIST datasets, while reducing power consumption by3.2×. They are at least3×more resource efficient than contemporary SNN architectures with comparable latencies.