A Cryo-CMOS 4–5.9-GHz Fractional-N Cascaded PLL Achieving 36.9-fsrms Integrated Jitter and −69.1-dBc Fractional Spur

This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.