Leak-CIM: A PVT-Robust and Energy-Efficient SRAM Computing-in-Memory Macro Exploiting Transistor Leakage

The binarized neural networks (BNNs) significantly reduce arithmetic and storage costs for edge inference, but repeated bitwise accumulation and memory access still limit system energy efficiency. This article presents leak-computing-in-memory (CIM), a256× 64static random access memory (SRAM)-based voltage-mode CIM macro that exploits the subthreshold leakage ofoff-state transistors as ultrahigh-impedance pseudo-resistors for low-energy analog accumulation. Unlike charge-sharing CIMs, the proposed scheme maintains a wide read-bitline (RBL) dynamic range while strongly suppressing the shoot-through current that typically limits voltage-mode operation. To compensate for the process, voltage, and temperature (PVT) sensitivity of leakage-based pull-up and pull-down paths, the leak-CIM employs a postfabrication N-well bias calibration scheme that restores their resistance balance. The postlayout simulations show that the calibrated macro maintains a normalized mean-squared error below1.12× 10⁻²across 40 global PVT conditions. Fabricated in a 22-nm bulk-CMOS process, the macro achieves up to 1799 TOPS/W and 31.67 TOPS/mm2across measured operating points. When the measured ADC characteristics are incorporated into a BNN inference model, leak-CIM attains 98.15% accuracy on MNIST and 86.04% on CIFAR-10.