A Hardware-Efficient Reed--Solomon Decoding Architecture for Single-Symbol Error Correcting in High-Bandwidth Memory

The JEDEC HBM3 standard mandates a (19, 17) single-symbol-error-correcting (SSEC) Reed-Solomon (RS) code with 16-bit symbols, requiring hardware implementations to satisfy stringent area and latency constraints. While SSEC decoding is simpler than general multisymbol correction, conventional architectures still rely on Galois field (GF) inverse operations, leading to substantial look-up table (LUT) overhead. This brief proposes an area-efficient, high-speed SSEC RS decoding architecture specifically optimized for the high-bandwidth memory (HBM) environment. By exploiting the short message length of the (19, 17) code, the proposed design restricts decoding operations to a limited set of GF elements, effectively eliminating the need for expensive GF inverse LUTs. Instead, error location and magnitude are determined through a comparison-based search and constant GF multiplications. Synthesis results in 28-nm CMOS technology demonstrate that the proposed architecture achieves up to 97% area reduction compared to conventional decoder implementations. Furthermore, it improves operating speed by up to 81% over algorithmic baselines. These results confirm the superior efficiency and scalability of the proposed design for highly integrated, latency-critical memory systems such as HBM3.