Reconfigurable In-Memory Computing With Compute-Fusion SAR ADC for Area-Efficient Pipelined MAC Operations

This brief proposes a reconfigurable compute-in-memory (CIM) macro using a compute-fusion successive approximation register ADC (CF-SAR) that integrates charge-domain multiply-and-accumulate (MAC), SAR quantization, and partial-sum accumulation in a unified data path. By reusing the capacitor array for both analog MAC and ADC conversion, the design reduces area overhead. A reconfigurable in-memory-computing storage and logic (RSL) element merges SAR result storage with in-memory serial addition (IMSA), enabling a pipelined ping-pong quantization/serial accumulation scheme without external digital adders. The macro supports 1-/2-/4-bit signed and unsigned weights viaand/nandselection and bank swapping without extra hardware. Implemented in 40 nm CMOS, the macro reduces transistor count by 44%, achieving up to 250.73 TOPS/W and 255.5 GOPS, with normalized efficiencies of 273.92 TOPS/W and 197.61 TOPS/mm2, and 98.54%/86.62% accuracy on MNIST/CIFAR-10.