A 1.25‐GS/s SAR ADC With Scalable Input and 3–6‐Bit Reconfigurable Resolution for Operation Unit‐Based RRAM–CIM Architectures

The operation unit (OU)‐based architecture is widely adopted in resistive random access memory‐based compute‐in‐memory (RRAM–CIM) macros. As the OU size may vary across different designs and under different workloads, the resolution‐reconfigurable analog‐to‐digital converters (ADCs) are required for better energy efficiency. To this end, this paper presents a 3–6‐bits reconfigurable asynchronous successive approximation register (SAR) ADC with an input‐scalable architecture. The proposed design supports resolution reconfiguration by scaling the bitline current that charges the sampling capacity dynamically according to the required computing resolution. Moreover, we utilize the upper‐plate sampling method to reduce settling time during the most significant bit phase and introduce an asynchronous control scheme combined with a high‐speed dynamic comparator to enable a short decision period. The proposed single‐channel SAR ADC is designed with a 28‐nm process, achieving 1.25‐GS/s sampling rate at 1‐V supply with only 0.85‐mW power consumption. Compared to the fixed‐resolution ADC, the proposed design achieves 13%–43% power savings by reducing comparison cycles and enabling early termination.