Key result
Self-adaptive SoC design improves memory utilization ~39% versus constant sample clocks for biomedical signal processing.
Why the study?
There is a high demand for low-power biomedical signal-processing schemes that occupy very little on-chip area for applications such as PPG, ECG, and BP measurements.
A novel low-power SoC design demonstrates efficient signal processing for PPG, ECG, and BP measurements with very low charge consumption.
May support efficient multi-parameter monitoring in wearables; leaves open clinical validation of the SoC.
In view of the high demand for low-power biomedical signal-processing schemes occupying very less on-chip areas, we propose a low-power highly integrated system-on-chip (SoC) design comprising a nonuniform biomedical sensing signal conditioning circuit and a 32-bit microprocessor. The proposed design is implemented using a 0.18 µm CMOS EFLASH process in an area of 4.2 mm2, and is applied in PPG, ECG and BP measurements. Experimental results show that our SoC design provides extremely good performances for sparse features of all three biomedical applications. The charge consumption is 25 mAh for three months, for an experimental board design including sleep current and junction leakage current.
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Ma et al. (2017) studied this question. Low-power highly integrated system-on-chip (SoC) design vs. Constant sample clock (no self-adaptive feature) was evaluated on Memory utilization improvement. The proposed self-adaptive system-on-chip design improved memory utilization by 39.29% compared to a constant sample clock without self-adaptive features for biomedical signal processing.
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