Key result
The proposed Biopotential processor designed in 0.18μm CMOS TSMC technology acquired 33005μm2 area, consumes 0.382mW power, and has a 16.89ns time delay.
The proposed biopotential processor offers high-resolution signal monitoring with low power consumption and small area for portable biomedical applications.
May support portable biopotential monitoring devices; leaves open clinical validation before practice adoption.
This paper presents the design of portable Biopotential processor for Electrocardiogram (ECG), Electromyogram (EMG), Electroencephalogram (EEG), Electrooculogram (EOG) signals monitoring device. This processor offers highresolution biomedical signals which can improve diagnosis and monitor the evolution of several diseases by suppressing baselines wander (0.1–0.5Hz) and power line interference noise (50/60Hz). It contains two memory segment Band Pass Memory Segment (BPMS) and Band Stop Memory Segment (BSMS) which will provide coefficients for band pass and band stop FIR filter respectively. It provides the control signal to bio-potential front end to switch between low noise-High CMRR mode and average noise-average CMRR mode. It also provides the control signal to successive approximation register (SAR) DAC. The proposed Biopotential processor is designed in Spartan-3E FPGA and 0.18μm CMOS TSMC technology. It has acquired 33005μm 2 area & consumes 0.382mW power. It is also verified with FPGA which consumes area with 282 numbers of 4 inputs LUTs and 16.89ns time delay.
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Senapati et al. (2017) studied this question. Biopotential processor was evaluated on Area, power consumption, and time delay. The proposed Biopotential processor designed in 0.18μm CMOS TSMC technology acquired 33005μm2 area, consumes 0.382mW power, and has a 16.89ns time delay.
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