Design Space Exploration of Partial Product Reduction Stage on 8x8 Approximate Multipliers

In the nano-scale era, the main objective of integrated circuits is to enhance speed while minimizing power consumption and area. This demand has given rise to the concept of approximate computing, which holds great significance in error-tolerant applications such as multimedia, machine learning, signal processing, and scientific computing. This research delves into the characteristics of various approximate reduced complexity Wallace multipliers, assessing their introduced error and area usage. In the present study, the approximation of the calculations is performed at the stage of reduction of partial products. This stage comprises several full adders, which were substituted with approximate full adders to introduce approximation. The study's findings emphasize that the introduced error and required area vary depending on the combination of approximate adders used, as well as on the placement of these adders in the partial product reduction stage. Utilizing a Genetic Algorithm (GA), we achieve a size reduction of our approximate multiplier to 54% of the exact multiplier. Additionally, by allowing the expansion of the size to 72% of the exact multiplier's area, we enhance the accuracy of the approximation by 32%. The suggested approach could assist designers in choosing the most appropriate amongst the available configurations of approximate adders for the partial product reduction stage in a reduced complexity Wallace multiplier, tailored to the specific requirements of their application.