In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf 0.5 Zr 0.5 O 2 by gate-side dielectric interlayer engineering. By inserting a 3 nm Al 2 O 3 dielectric interlayer between TiN gate metal and ferroelectric Hf 0.5 Zr 0.5 O 2 , we achieve a memory window of 4.1 V with endurance of ~10 4 cycles and retention over 10 years. The physical origin of memory window enlargement is clarified to be charge trapping at the Al 2 O 3 /Hf 0.5 Zr 0.5 O 2 interface, which has an opposite charge polarity to the trapped charges at the Hf 0.5 Zr 0.5 O 2 /SiO x interface.
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Hu et al. (2024) studied this question.
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