Low-Power VLSI Architecture for Ternary Galois Field

The cost of sending and receiving data has increased. Hence, storing and keeping the information secured has become more complex. This requires a secure connection in every application. Cryptography is one such possible solution that secures the data. In the modern world, cryptography is helpful in numerous applications such as social networking, Email, and ecommerce, in addition to defence-related ones. In predesigned interfaces like embedded systems, cryptography is the critical component. Most of the cryptographic algorithms, such as Advanced Encryption Standard (AES) and Elliptic Curve Cryptography (ECC), use modular operations involving Galois Field (GF) (pm ), where 'p', the base of the modular operations, is a prime number and 'm' represents the power. This research focuses on implementing the Ternary Galois Field (GF) (3m ) using the Forced Stack technique with low leakage power. Ternary Galois field implementation using the proposed Ternary Multiplexers and Ternary gates using the canonical expression is compared. This comparative analysis for different designs helps choose the best-optimised implementation methods concerning the number of ternary logic gates, transistors, and leakage power. Further, using the implemented Ternary Galois field elements, a module adder circuit is designed and implemented using a heuristic approach in Cadence Virtuoso.