Flip-Chip Bonding for SiC Integrated Circuits With Gold Stud Bumps for High Temperature Up To 600 °C Applications

This work studies a 3-D stacking approach to silicon carbide (SiC) integrated circuit (IC) chips using flip-chip technology with gold (Au) stud bumps for high-temperature (up to 600 °C) applications. Standard photolithography, sputtering deposition, and lift-off process were used for chip metallization and patterning with titanium (Ti), tantalum silicide (TaSi2), platinum (Pt), and Au thin films. Au stud bumps were used to bond the SiC dummy chips with a flip-chip die bonder. Die shear tests were conducted, and the electric resistance of the daisy chain interconnect between the chips was measured before and after thermal aging in the air at 600 °C for up to 12 days. It is found that the electric resistance of the daisy chain interconnects decreases and stabilizes at about <tex-math notation="LaTeX">1 Ω </tex-math> for 36 bumps, showing that the thermal aging process improves the electric performance of the interconnect with Au stud bump bonding by reflowing and annealing the metals. The destructive die shear test shows that, with thermal aging, the shear force decreases for the chip stacks and stabilizes at about 15 gram force (gf) per bump with the TaSi2 diffusion barrier in the metallization. In contrast, the shear strength increases for the chip stacks without the TaSi2 barrier in the metallization.