Jitter Reduction for Multi-GHZ ATE Up to 20 GHZ

This paper describes methods for reducing random jitter (RJ) of clock signals in multi-GHz automated test equipment (ATE). The methods are based on real-time averaging of parallel/synchronized signals with largely uncorrelated RJ. Prior work (up to 10 GHz) is extended by demonstrating applicability to frequencies up to 20 GHz with resulting RJ less than 200 femtoseconds (fs). The theory of operation is reviewed and experimental results are shown for 10, 12, 18, and 20 GHz. A de-embedding procedure is used to separate the jitter contribution of the test instruments (jitter "floor") from the measured values to obtain a close estimation of the actual ultra-low jitter values of the measured signals.