A Study on Floating Gate Profile Control and Reliability Improvement in Planar 1XNM Nand Flash

As the critical feature size shrinkage on planar 2D NAND flash, conventional N-type poly silicon using as floating gate cannot meet the requirement for higher cycling performance. Electric trap in tunnel oxide during cycling further made cycling window margin. Using P-type poly silicon to replace N-type poly silicon showed great benefit for reliability improvement, because hole-injection features of P-type poly silicon floating gate can minimize Vth shift. However, continuous design pitch shrinkage and boron-dopants in P-type poly silicon both made gate poly etching process more challenging. In this work, profile control and selectivity optimization for poly gate etching are studied by adjusting each etching step with variable gas ratio, source/bias power ratio and power delivery methods. As a result, better floating gate profile without silicon oxide fence and silicon pitting was achieved, and reliability performance showed significant improvement.