The Influence of Metal Barrier Punch Through Process on Dielectric Reliability at 55 nm CMOS Node

The influence of metal barrier punch through process on electrical property, dielectric reliability and failure mechanism is investigated for copper (Cu) interconnect with TaN/Ta metal barrier layers, using via first (VF) and trench first (TF) dual damascene (DD) process. It is found that with improved cross-section profiles, the optimized integrations show not only smaller via/line resistances due to the reduction of barrier thickness, but also an improvement in breakdown voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd</inf> ) by preventing Cu from penetrating into the dielectric layer at the line bottom, and thus enhancing the reliability of interlevel dielectric layers.