Evaluating 224G SI Performance of Vertical Interconnections on Package Substrate and PCB

224G is the next generation SerDes technology to meet the data traffic demand in data center, and the standard groups of Ethernet and OIF are leading the creating of 224G PAM4 related specification. As the data rate is increased from 112Gbps PAM4 to 224Gbps PAM4, the signal Nyquist frequency will be doubled, increased from 28GHz to 56GHz, the channel bandwidth requirement will be increased too, maybe up to 84GHz(0.75*fb). As the 224G signal bandwidth increasing, the wavelength of the signal high frequency components can be comparable with the size of vertical interconnection structures in package(PKG) substrate and print circuit board (PCB), like the plated through hole(PTH) via and the stacked laser via in package substrate, the PTH via in PCB ball grid array (BGA) area and connector pin area. The high frequency characteristics of the electrical channel will be dominated by these vertical interconnection structures, like the channel bandwith(BW), the return loss(RL), the crosstalk, etc. This paper attempts to demonstrate the high frequency characteristics of vertical interconnections of the current 112G PAM4 design, and to explore the solutions to improve the high frequency performance of the vertical structures for the upcoming 224G PAM4 signaling, like the channel BW/IL/RL/erosstalk.