As during the idle or clock gated mode, long term DC-stress condition in the timing signal path could result in an obvious waveform change induced by aging degradation, which could bring about timing violation and reliability issue. In this paper, we rely on two cases to reveal and study the impact of long term DC-stress on waveform by means of SPICE simulation. Furtherly, according to the simulation results, some measures are proposed to avoid such waveform change-induced aging timing issues.
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Wang et al. (2024) studied this question.
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