Duty-cycle-aware empirical modeling of BTI-induced delay degradation in FPGA LUTs

As Field-Programmable Gate Arrays (FPGAs) adopt advanced CMOS nodes, Bias Temperature Instability (BTI) becomes an important threat to timing reliability. This paper investigates aging-induced delay degradation in SRAM-based FPGA Look-Up Tables (LUTs), with emphasis on stress duration and signal duty cycle. A representative transmission-gate LUT topology is analyzed through SPICE simulations to identify NBTI- and PBTI-sensitive timing paths, and a 65 nm Cyclone III FPGA is characterized for 3000 h under an accelerated core-voltage condition. An aggregate empirical model, expressed using path-level coefficients A – H , static-path terms X and Y , and a common time exponent n , is calibrated to the measured rise- and fall-delay shifts. The same 3000-hour dataset is used for both parameter estimation and fit assessment; consequently, the reported error metrics quantify in-sample goodness of fit rather than independent predictive validation. The measurements show a pronounced duty-cycle-dependent asymmetry between rise and fall degradation, consistent with PMOS-dominated NBTI stress and recovery. The resulting framework connects transistor-level path interpretation to a compact circuit-level description under the tested accelerated condition; extrapolation to other voltage and temperature conditions requires additional characterization.