Comparative Study of Nanowire FET & Internal Gate Nanowire FET

In the context of scaling CMOS devices, various geometries have been proposed. This research examines the performance comparison between a standard 5-nm gate length Nanowire Field Effect Transistor (NWFET) and an NWFET with an Internal Gate. The study evaluates key parameters such as on-state current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> ), off-state current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), and I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ratios to assess the performance of these devices. Notably, the investigation focuses on the impact of incorporating an inner gate within the structure. This inner gate structure exhibits lower SS and DIBL values, indicating enhanced control and improved short-channel behavior. The exceptional electrical performance of the internal gate design underscores its potential to augment subthreshold properties, thereby facilitating further advancements in device scaling.