Hardware evaluation demonstrates reduced complexity and high throughput in massive MIMO detection, highlighting enhanced gate and area efficiency for advanced wireless receivers.
When faced with challenging antenna configurations or high-order modulations in realistic propagation environments, the Belief Propagation (BP) MIMO detector outperforms its linear counterparts. To mitigate the error floor issue and lower the complexity, a revised BP detector, named the Belief-selective Propagation (BsP) detector, has recently emerged by selectively utilizing trusted incoming messages for updates. Despite those promising potentials, the straightforward hardware implementation of the BsP detector still suffers from high complexity and necessitates further optimization. To bridge the gap between the BsP algorithm and implementation, this paper introduces an approximate but implementation-friendly BsP detector called aBsP, based on which the very first BsP hardware is proposed. Two unexplored features: approximate initialization and simplified message updates save the complexity (more than <tex-math notation="LaTeX">$84$</tex-math> %) with acceptable performance penalization. Multi-level optimization techniques involving group-layered message updating, approximate arithmetic circuits, and hybrid-precise quantization are developed to boost the hardware efficiency A <tex-math notation="LaTeX">128× 8</tex-math> <tex-math notation="LaTeX">$256$</tex-math> -QAM aBsP MIMO detector ASIC in <tex-math notation="LaTeX">$40$</tex-math> nm CMOS occupies an area of <tex-math notation="LaTeX">$0.68$</tex-math> mm <tex-math notation="LaTeX">²</tex-math> and reaches a throughput of <tex-math notation="LaTeX">$790.52$</tex-math> Mbps. Benchmarking with the recent arts, this work achieves <tex-math notation="LaTeX">1.08×</tex-math> area efficiency and <tex-math notation="LaTeX">3.34×</tex-math> gate efficiency.
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Zhou et al. (2024) studied this question.
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