Accelerating Real-Valued FFT on CPU-FPGA Platforms

The real-valued fast Fourier transform (RFFT) is an ideal candidate for implementing a high-speed and low-power FFT processor because it only has approximately half the num-ber of arithmetic operations compared with traditional complex-valued FFT (CFFT). Although RFFT can be calculated using CFFT hardware, a dedicated RFFT implementation can result in reduced hardware complexity, power consumption and increased throughput. However, unlike CFFT, RFFT has irregular signal flow graphs which hinders the design of efficient pipelined archi-tectures. In this paper, utilizing Open Computing Language (OpenCL), we propose a high-level programming method for the implementation of pipelined architectures of RFFT on FPGAs. By identifying the regular computational pattern in the flow graph of RFFT, the proposed method essentially uses a for loop to implement the RFFT algorithm, and later with the help of high level synthesis tools, the loop is fully unrolled to automatically build pipelined architectures. Experiments show that for a 4096-point RFFT, the proposed method achieves a 2.49x speedup and 3.09x better energy efficiency over CUFFT on GPU, and a 21.12x speedup and 16.09x better energy efficiency over FFTW on CPU respectively. Compared to Intels CFFT design on the same FPGA, the proposed one reduces 12% logic resources and 16% DSP blocks respectively, while achieving a 1.48x speedup.