PANEL: EDA Challenges at Advanced Technology Nodes B

PPA (Performance, Power, and Area) is our goal. Although most people no longer pursue top speed, it is still very important. When reducing power and area, a common side effect is that timing gets worse. Low power/area method never makes speed faster. Once the speed slows down, buffering or up-sizing is inevitable. The difference between previous tech nodes is the gap between global and detailed placement (GP and DP). More and more rules make gap growing. Once DP cannot make most instances to stay original place, expectation of global placement will be disappointed. GP or more buffering will be necessary again. Physical-rule awareness will be a necessary improvement for GP/buffering. We will list some of the challenges how advanced nodes face.