Simulation study demonstrates trap generation in 3D NAND flash tunnel oxide during cycling, highlighting degradation under varied bias and temperature stress.
The Physical TCAD models, which have been validated for the aging of logic devices, are utilized to simulate trap generation (TG) in a memory device during program/erase (P/E) cycling. The models are similar to ones describing Positive Bias Temperature Instability (PBTI) for Program and Negative Bias Temperature Instability (NBTI) for Erase. A generic Reaction-Diffusion-Drift (RDD) model is used to simulate trap generation in the tunnel oxide of 3D NAND flash memory cells during P/E cycling. The impact of cycling for different P/E bias conditions and bake temperatures have been explored using a two-dimensional (2D) cross-section of a 3D NAND flash memory string.
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Kumar et al. (2024) studied this question.
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