Self-heating poses critical reliability concerns in the nanoscale transistors. It leads to carrier scattering, which, affects the Device Figure of Merits (FOMs). The degradation in the device performance worsens when traps are present in the device. In this paper for the first time, we have investigated the impact of interface traps (N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</inf> ) available at the BOX -channel, as well as at the oxide-channel interface in the n-PDSOI transistor. Using well calibrated TCAD models our results demonstrate that 1. The output characteristic of PDSOI transistor shows a Negative Differential Resistance (NDR) due to BOX-channel interface traps; 2. The BOX-channel traps causes traps early ageing. 3. Combinedly these traps deteriorate the device FOMs and using a semiempirical model the cause of NDR is also presented.
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Kumar et al. (2024) studied this question.
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