Scaling Options for GAA Nanosheet Based Devices: Role of Decoupling Inner- and Outer-Gate Lengths

Using a full device-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner (LG(I))- and outer (LG(O))- gates in gate-all-around nanosheet FETs. A better trade-off between short-channel effects (SS A T), external resistance (REXT), effective favors for a more aggressive LG(O) scaling (reduces C CARA and/or relaxes contact length, LCNT) keeping LG(I) relaxed (controls REFF, SSAT). Up to 10% speed-at-iso-leakage, 11% speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this design, in addition to allowing better contact-poly pitch (CPP) scaling path.