Design of a Fast Chirp PLL Using Digital Phase Interpolator

This study proposes a phase-locked loop using a two-point modulation technique for fast chirp generation. The frequency synthesizer consists of high- and low-pass regions. In the high-pass region, continuous frequency modulation was achieved using a charge digital-to-analog converter, while a self-calibration block compensates for the nonlinearity of the voltage-controlled oscillator. In the low-pass region, the synthesizer is locked to the desired frequency with a low spurious level using a divider, delta-sigma modulator, and digital phase interpolator. The design used a 28 nm CMOS process and consumed 32 mW power. The chirp bandwidth is 960 MHz with a chirp duration of 41.6 μs. The slope of the chirp is 21.3 MHz/us, with a root mean square error of 3.7 MHz.