10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS

A frequency-modulated continuous-wave (FMCW) chirp generator serves as the pivotal building block for short-range 3D imaging radar systems, which have been widely utilized in medical and security applications. To enable quick and precise scanning with sub-millisecond snapshot duration and sub-centimeter depth resolution in a 79GHz large-scale MIMO radar imaging system, which composes of hundreds of TX/RX elements, the FMCW chirp generator must generate chirps with about 1 μ s chirp duration and operate >15 GHz bandwidth (BW), necessitating an ultra-fast chirp slope exceeding 15GHz/μ s. Meanwhile, high chirp linearity and low phase noise (PN) are also essential to improve the signal-to-noise ratio (SNR) for high-quality imaging, and the between-chirp idle time (Tidle) must be shortened to 50ns given that at least 95% of the chirp duty-cycle is required. To resolve the contradictions between narrow PLL BW for low PN and quick loop response for fast chirp, two-point-modulation (TPM) technique is widely implemented in fractional-N PLLs [1–5]. Regarding the linearity of an ultra-fast wideband chirp, it is challenging to effectively compensate for the residual frequency error (Fₑᵣᵣₒᵣ) of a 1 st -order digital pre-distortion (DPD) [2–4] and the ramp non-linearity of a ramp tracker [1, 5] with an insufficient PLL bandwidth, calling for advanced curve fitting techniques. In this work, to diminish rms F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">error</inf> in the context of ultra-fast wideband chirp generation, a ramp-tracker assisted 2 nd -order curve-fitting (2 nd -CF) DPD is proposed in a fractional-N sub-sampling (SS) PLL, achieving an 11GHz fast saw-tooth chirp with a 2.3GHz chirp bandwidth, 2.3GHz/μ s chirp slope, and 0.051% rms Fₑᵣᵣₒᵣ. Leveraging an integral path in the digital loop filter (DLF), dynamic track-and-hold functionalities are realized in the voltage tracking loop (VTL) for robust LUT calibration. Advanced phase control is investigated in a DTC modulator to eliminate the fluctuation of the loop locking voltage during large frequency hopping (>20% of the center frequency f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">center</inf> ), which further secures 50ns T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">idle</inf> .