A Low Power Frequency Synthesizer Design for RF Wireless Power Transfer Applications

This paper describes the design of a low power 5.8 GHz phase-locked loop (PLL) that can be used as the frequency synthesizing block in a wireless power transfer transmitter chip for Internet of Things (IoT) charging application. The paper covers the design and simulation of a high-speed phase frequency divider, charge pump, wide-band VCO, and a highspeed frequency divider chain. Design calculations are carried along with circuit simulations and results. All simulations were done on Cadence Virtuoso using the 65 nm TSMC CMOS technology. Circuit parameters including output frequency, locking time, power consumption, and jitter are simulated to verify the design specifications. The phase noise of the VCO was −114.6 dBc/Hz at 1 MHz offset. the synthesizer is evaluated based on single blocks noise performance. The designed synthesizer was able to lock to the desired 5.8 GHz in less than 8 µs with a total power consumption of the 8.04 mW under 1 V supply voltage.