Study of energy-efficient phase-locked loop for high‑frequency analog applications

In this paper, it is proposed an improved phase locked loop for analog applications which performs better in terms of power dissipations, frequency of operation and lock in time. In the proposed phase-locked loop (PLL) circuit, a double‑edge triggered phase-frequency detector (PFD) in the forward path and an additional voltage-controlled delay line (VCDL) in the feedback path have been used. Due to these modifications the lock in time (hence speed), frequency resolution, jitter performance is improved and power is optimised. To optimise power performance, the proposed PLL is designed using 18-nm FinFET technology. As the proposed circuit incorporates VCDL to assess its impact on transistor count and area, the layout design and DRC/LVS checks were completed. Performance of proposed circuit is compared with existing CMOS‑based PLL and it is observed that proposed FINFET-based PLL consumes maximum of 74μW power at 5 GHz, lock in time of 27.5ns, output frequency of 4.4 GHz at reference frequency of 5 GHZ and area is 285 μm. The components used in all the circuits operate at a single supply voltage. Many IoT and especially SoC processors have low‑power constraints, which makes this structure appropriate.