A 28.8-to-43.2 GHz 79.8 fsrms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration

Millimeter-wave (mmW) phase-locked loops (PLLs) prefer large loop bandwidth for suppressing more voltage-controlled oscillator (VCO) phase noise, which, in turn, degrades the level of rejection to reference spur. This article proposes a complementary mixing phase detector (CMPD) to relax the above tradeoff through the spur compensation technique. Distinct from traditional RC filtering, the CMPD realizes spur reduction by mutual harmonic rejection whose effectiveness is enhanced by a foreground calibration. It also neutralizes charge injection and clock feedthrough without consuming extra power, while enabling frequency detection and lock detection. Fabricated in a 28-nm CMOS technology, the PLL achieves a frequency tuning range (FTR) of 28. 8-to-43. 2 GHz, - 78. 5-dBc reference spur, and an rms jitter of 79. 8 fs ₑ₌ₒ (from 10 kHz to 100 MHz), with a jitter-power figure-of-merit (FoM) of - 250. 0 dB.