Thermal Modeling of E-Mode GaN HEMTs under Wide-Range Thermal Cycling Tests

This paper presents a thermal modeling technique for 650 V / 7.5 A GaN HEMTs under accelerated thermal cycling (ATC) tests. The thermal modeling validates the limitations caused by the slow response of the commercial thermal sensors (i.e., thermistor) used for monitoring the junction temperatures (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> ) of GaN HEMT devices under test (DUTs) in wide thermal cycling tests. The proposed technique utilizes experimental results captured during a thermal runaway scenario to analyze the non-linear dissipated power pattern in ATC from the DUT into the ambient environment. Hence, the thermal equivalent circuit of the GaN board under test consists of RC (or thermal time constant) networks of the main components involved in the heat dissipation pathway from the DUT's junction channel into the thermistor, including GaN DUT, PCB, and the thermal sensor. The analysis reveals the challenges of using traditional thermal sensors to monitor the DUT's junction temperature under ATC testing, where the thermal sensor (i.e., thermistor) contributes to about 4 s time constant, which is significantly higher than the thermal transient time of the GaN DUT. The proposed modeling and experimentation techniques are able to expose and quantify the vulnerabilities of the GaN DUT to a thermal runaway, especially when the DUT is cycled with high T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf> limits (>125 °C).