An enhanced all-digital CMOS capacitor-type pulse-varying mechanism for low-cost wide-range time-to-digital converters

This paper introduces an all-digital CMOS enhanced capacitor-type pulse-varying (shrinking) mechanism designed to improve resolution for low-cost wide-range time-to-digital converters (TDCs). The mechanism utilizes a size-ratioed MOS capacitor coupled with homogeneous gates within the delay line, functioning as a pulse-varying cell to achieve time attenuation and improved time resolution. Unlike a previous capacitor-type mechanism, the proposed approach employs a longer channel length to extend the measurement range while maintaining high time resolution. It offers the advantages of linearly varying resolution and resolution enhancement. This study avoids time-consuming full-custom CMOS design, opting for a fully digital CMOS approach using a TSMC 0.35-μm CMOS process. After circuit layout and HSPICE simulation, the experimental results demonstrate the benefits of a simple structure and resolution enhancement while maintaining lower cost and an expansive measurement range for TDC applications.