VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study

VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study Abstract Although the Cadence Virtuoso has been widely used in many universities, there is lack of a shareable publication, document, or tutoring video on the very large-scale integration (VLSI) design, verification and fabrication. Few online tutorials or tutoring video are quite outdated. They either cannot be used for step-by-step guideline, or they only cover part of the entire design flow, which doesn't meet designer's need. The lack of up to date publication or document has caused a huge barrier for universities to teach a VLSI lab. Due to a severe discrepancy in procedure and parameter setting, instructors have to report technical cases to the Cadence technical support center, and then spend significant time troubleshooting problems with the remote assistance from the Cadence engineers. This has greatly affected the progress of lab teaching and student learning. In addition, there is very few sources of educational tutorials of adding pad frame, which is a complex but extremely important component before fabrication. Therefore, there is an urgent need to create and disseminate a shareable publication or document on VLSI design, verification and fabrication with the latest version of Cadence Virtuoso. This paper promotes the needs of a comprehensive study on the newest version of Cadence Virtuoso, a state-of-the-art CAD tool for VLSI design. An 8-bit arithmetic logic unit (ALU) is used as a proof-of-concept example to go through the major VLSI design flow, including schematic capture, pre-layout simulation, physical layout, extract, design rule check (DRC), and layout vs. schematic (LVS). In addition, since this specific ALU is designed to perform three logical operations (i.e. AND, OR, and XOR) and two arithmetic operations (i.e. addition and subtraction), their respective schematic, symbol, testbench, pre-layout simulation, physical layout, post-layout simulation results are demonstrated with detailed snapshots. Moreover, the design layout is wired to a 40-pin MOSIS Tiny Chip pad frame. The ALU circuit is then simulated along with the pad frame and the simulation results are analyzed. Universities and designers around the world will find it an invaluable document, which ensures an efficient and fast VLSI design, verification and fabrication using the latest Cadence Virtuoso software.