Design and evaluation of a 200 MS/s Artix-7 FPGA-based ADC prototype

This paper presents a 200 MS/s analog-to-digital converter (ADC) based on a multi-chain merged time-to-digital converter architecture, implemented in a Xilinx Artix-7 FPGA. The calibrated system achieves 1.17 mV vertical resolution across a 0.05–2.35 V input range and 7.1 effective number of bits at 1.13 MHz. The developed ADC further demonstrates single-photoelectron (SPE) detection capability when interfaced with a photomultiplier tube, and maintains linear response up to 30 PEs. These results suggest potential applications of FPGA-ADC technology in photoelectrical detection systems as an alternative to conventional commercial ADC chips.