Experimentally demonstrates that a distributed receiver array reduces multipath effects and improves interference suppression in wireless networks, suggesting a key advance for low-cost platforms.
This work presents a self-synchronizing distributed receiver array employing a dual-loop analog phase-locked loop (PLL) with a 4.6 GHz acquisition bandwidth, fabricated in 0.13 μm SiGe BiCMOS technology. The chip enables low-latency frequency synchronization and direct binary phase-shift keying (BPSK) demodulation, supporting coherent operation across spatially distributed nodes while reducing system complexity—a key advantage for low-cost platforms. Experimental results validate the array’s ability to suppress interference and mitigate multipath effects, demonstrating significant improvements in bit error rate (BER) and error vector magnitude (EVM) in challenging wireless environments.
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Kiyaei et al. (2025) studied this question.
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