Throughput optimization of NIL for the fabrication of advanced devices

Computational technologies and Electronic Design Automation (EDA) methods are still in the course of development for nanoimprint lithography (NIL). Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106 . In this paper, we introduce the methods used to create drop patterns and refinements to the NIL process simulator which can be applied to predict resist filling and, in the future, be used to make corrections to the drop pattern virtually, thereby eliminating time consuming on-tool verification. The models were then applied to better understand resist spread and filling, which play a significant role in NIL throughput. Two process related methods were also applied to enhance resist filling. The first involves the use of CO2 as an ambient gas. The second involved the application of solvent-enhanced resists designed to promote resist spreading. This paper reports the modeling predictions and the experimental verification of the models. The results indicate that throughput can be enhanced to 110 wafers per hour, an increase of almost 40%.