Enabling curvilinear masks: novel mask qualification methodology and experimental verification

As emerging technologies continue to reshape our world towards more sustainable and greener solutions, the global demand for advanced semiconductor devices is growing rapidly. To ensure these technologies remain accessible, it is crucial to address the cost of semiconductor manufacturing. Optical lithography, a key step in the semiconductor manufacturing process, significantly contributes to both cost and complexity. Therefore, the industry must leverage all available mechanisms to maintain high yield and control costs. One such mechanism is the adoption of curvilinear masks. Curvilinear masks, characterized by their non-Manhattan geometries, represent a significant advancement in photomask technology. These masks offer notable benefits, such as enhanced wafer process windows, decreased mask variability, and improved mask relaxation for specific applications like Via C2C. By reducing process complexity and improving mask performance, curvilinear masks can positively impact semiconductor chip yield. The challenges to their effective implementation have largely been resolved, and the industry is gearing up for their adoption. There is a pressing need for efficient and cost-effective methods to define specifications and qualify these masks, which can be achieved through CD SEM metrology. Gauge-based approach using generic test patterns akin to those for conventional Manhattan masks is discussed. The proposed methodology and test patterns exhibit the necessary sensitivity to mask critical dimensions and curvature, offering a cost- and time-effective solution for integrating curvilinear masks into IC manufacturing. This paper addresses the analysis of generic curvilinear test patterns, verification of generic test patterns using Logic and DRAM post curvilinear OPC and ILT test clips for upcoming technology nodes.