Modeling Analysis of Passivation and TEOS Cracking in BEOL Metal Trace Design

As flip chip packaging technologies advance, silicon-level failure highlights the importance for robust design evaluation methodologies early in the development cycle. To support this need, we have developed a multi-scale finite element analysis (FEA) framework that includes both 3D and 2D multi-scale simulations, to capture stress distributions at critical failure locations. These models demonstrated comparable stress trends, validating their effectiveness in identifying high-risk regions. To further investigate micro-crack propagation risks at submicron scales, a 2D fracture mechanics model is introduced. This model enables detailed analysis of how key design parameters, such as aluminum pad (AP) spacing and BEOL metal trace spacing, influence failure susceptibility. Notably, these parameters exhibit opposing effects on two different failure modes, underscoring the importance of trade-off analysis. This paper presents a simulation-driven framework for assessing chip-level failure risks during the early stages of silicon-level design. Rather than prescribing specific design solutions, this study emphasizes the use of developed modeling framework to guide early-stage design exploration on silicon-level failure risk. The modeling framework provides a foundation for integrating modeling-driven insights into silicon-level design and process development, ensuring robust chip design to avoid failures downstream in packages.