Test Chip and Finite Element Analysis of Passivation Cracking in Molded Integrated Circuits

Plastic-encapsulated microcircuits (PEMs) typically encounter high thermomechanical stresses during any thermal excursion due to the thermal mismatch between silicon, leadframe, and molding compound. The ensuing tractions on the devices can be sufficiently severe to crack the thin film layers, leading to electrical leakage and other reliability concerns. In this paper, a specially designed thin film cracking test chip is used to confirm the validity of various structural thin film models using Finite Element Analysis (FEA). Two key stress components were analyzed in these studies. 1) Global die surface shear stresses (Δτg) were estimated from 3-D FEA models of the package structure, allowing critical fracture threshold levels to be determined by comparison with empirical test chip data. 2) Local von Mises stresses (σL) were calculated from 2-D FEA models of the thin film sub-structures. Statistical analysis of these results reveals the relationship between these stress components and the structural influence of the thin film architecture and layout.