Analysis shows gate voltage impacts random telegraph noise amplitude in bulk CMOS devices at ambient and cryogenic temperatures.
Random telegraph noise (RTN) in 65 nm technology bulk CMOS devices was measured at both 300 K and 1.5 K, and the dependence of noise amplitude on gate voltage was analyzed. Considering the highly random nature of RTN, 1,024 devices of both nMOS and pMOS types were measured using addressable transistor arrays to obtain statistically meaningful results. It was confirmed that the single-trap RTN amplitude is in good agreement with the number-plus-correlated-mobility fluctuation model at both 1.5 K and 300 K for both device types. It is shown that, from the extracted model parameters, it is possible to gain information on trap location and single charge scattering behavior. The effects of series resistance on the model are also discussed.
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TAKEUCHI et al. (2025) studied this question.
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