Large scale gate-all-around MoS2 transistors array by lossless monolithic 3D integration

Integrating two-dimensional (2D) materials into three-dimensional (3D) architectures can break through the physical limits of materials in advanced processes. However, challenges such as severe interfacial doping caused by dielectric deposition during vertical stacking processing have led to performance degradation in MoS2 3D gate-all-around (GAA) field-effect transistors (FETs), thereby severely hindering their large-scale integration. Here, we demonstrate a lossless monolithic 3D (M3D) integration process flow enabled by an interface engineering strategy to achieve highly uniform large-scale integration of multi-channel MoS2 GAA FETs with ultra-high current density. This strategy involves reducing interface states and dielectric doping by forming van der Waals contacts with MoS2 and creating hydrophilic surfaces for high-κ dielectric deposition via an Sb2O3 layer, thereby significantly improving the performance of the GAA FETs. Statistics of 112 GAA devices exhibits record-breaking performance, including an average on-state current density of 227 μA/μm with a peak value exceeding 335 μA/μm, and an ideal minimum subthreshold swing approaching 60 mV/dec, all outperforming conventional back-gate transistors and other MoS2 3D FETs. Furthermore, TCAD simulation confirms that GAA FETs exhibit a 46% reduction in RC delay compared to planar structures, further demonstrating enhanced gate control. This work establishes a manufacturing pathway for achieving interface-doping-free deposition of gate dielectric layers, thereby addressing the performance degradation issue caused by repeated processing steps in high-density M3D heterogeneous integration.