An Area‐ and Energy‐Efficient RRAM‐Based 6T1R Non‐Volatile SRAM Cell for Edge Devices

This work proposes a 6T1R non‐volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage‐division (VD)‐based restore process with reduced DC current and (3) a trimmable multi‐cycle (TMC) store process to reduce data backup and recovery errors. We fabricated a 1 kb VD‐6T1R nvSRAM test array with back‐end‐of‐line integrated metal oxide RRAM cells in a 180 nm CMOS process. The reuse of transistors allows the VD‐6T1R cell structure to occupy only 1.14× the area of a standard 6T SRAM cell. The store and restore operations were experimentally verified at the array level. The restore error rates of the fabricated test array can be effectively suppressed using TMC store cycles. The restore errors in the fabricated 1 kb cell array can be eliminated after five cycles.