Analysis of Test Access Mechanisms for Improving Scan Compression and Test Time

System-on-Chip (SoC) devices now integrate dozens—and sometimes hundreds—of heterogeneous embedded IP cores, each of which must be verified after fabrication. Industry therefore relies on modular testing so that every core can be exercised and validated without revealing its internal implementation, and so that designers can reuse test patterns efficiently. A persistent challenge is the mismatch between the limited scan-in/scan-out bandwidth at the chip boundary and a much larger channel capacity required if all cores were tested simultaneously. Widespread use of scan-compression schemes, such as Embedded Deterministic Test (EDT), offers several features for channel count selection, and this also needs to be considered during bandwidth allocation across cores. The multiple requirements are met using Test Access Mechanism (TAM), and over the past two decades, researchers have proposed many TAM architectures that move well beyond simple pin multiplexing, each balancing wiring overhead, concurrency, pattern compression, and scheduling complexity in different ways. However, a combined study of their effectiveness considering multiple aspects is not available. This study reviews the principles, algorithms, and architectures of TAM and test scheduling techniques. A classification of the techniques is provided, based on the method used and the area of application. The goal of the study is to create a platform for the future development of test access mechanisms. The study is believed to be helpful to both industry and academia.