This paper presents a countermeasure for security in System-on-Chips, reducing vulnerabilities in streaming scan networks.
The increasing complexity and core count of modern System-on-Chips (SoCs) have raised significant concerns regarding test time and test data volume. Despite advancements in SoC design, the physical size of SoCs remains relatively constant, imposing stringent constraints on the number of additional I/O pins to support parallel testing. Furthermore, the disparity in scan chain lengths exacerbates these challenges due to padding requirements, which significantly increase the test data volume. Recently, a novel test architecture, the Streaming Scan Network (SSN), has been introduced, which demonstrates a significant reduction in both test time and test data volume. However, the SSN lacks robust security countermeasures, making it susceptible to threats such as unauthorized access and data tampering. To mitigate these threats, this paper presents a lightweight and inherently secure solution that leverages the IJTAG Static Test Data Register (TDR) as a dual-functional module, ensuring both security and the preservation of the SSN’s original functionality. The experimental results demonstrate that the proposed countermeasure incurs 9.08%, 18.34%, 77.54% and 167.28% less area overhead compared to the state-of-the-art Masking, NLFSR, UAU and ROT countermeasures, respectively, while maintaining a security level equivalent to a 1024-bit key. Additionally, the proposed approach maintains low computational overhead and minimal authorization cycles, making it a scalable and practical solution for secure SoC testing.
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Kumar et al. (2025) studied this question.
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