Development and Performance Analysis of High-K Spacer-Induced Strained Si/SiGe Channel-Based Gate All Around FET for Thermal Effects

A Gate Stack GAA FET using SiGe with a 2 nm gate underlap encapsulating a high-k spacer has been created, explored, and evaluated for improved performance in radio frequency applications. The chip shows significant improvements in electrical and radio frequency analog performance because of the use of wrapped underlaps of high-k, which suppress parasitic capacitance and fringing field effects, to achieve a 192.52% boost in drain current and 98% reduction in IOFF current, translating into better performance. This new device, as proposed, has demonstrated improved switching behavior with the ability to reduce subthreshold swing by about 11.24% and results in a better Ion/Ioff ratio over existing devices, while also maintaining efficient control over other SCEs, with it being well-suited for the implementation of high-performance and low-power CMOS circuits. In addition, linearity parameters like VIP2, VIP3, and IIP3 reflect improvements, with the device having lesser harmonic distortions (IMD3 and THD), therefore making it more appropriate for RF and analog circuit uses. These results point to the prospect of SiGe-based Gate Stack GAA FETs with a 2 nm gate underlap encircling a high-k spacer for low-power, high-speed applications in IoT and 5G/6G technologies toward building environmentally friendly and sustainable electronic solutions.