Scalable self-aligned fabrication of nanoscale vertical a-IGZO TFTs utilizing angled deposition

Amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) are promising for nanoscale logic and memory devices, including vertical-channel and monolithic 3D DRAM, owing to their high mobility, uniformity, and compatibility with low-temperature processing. However, nanolithographic definition of a-IGZO channels remains difficult because of their sensitivity to plasma damage and the poor volatility of In, Ga, and Zn etch by-products. Here, we present a scalable self-aligned fabrication strategy that exploits the shadowing effect of angled deposition to realize nanoscale devices without utilizing nanolithography. Using this method, we examined top-gate-top-contact device (TGTC), the widely adopted baseline that suffers from plasma-induced damage and top-gate-bottom-contact device (TGBC), which mitigate channel plasma exposure but undergo severe contact oxidation during post-deposition annealing (PDA). To overcome these limitations, we developed a nanoscale vertical TFT architecture in which obliquely deposited Ni/Au electrodes directly form self-aligned source/drain contacts without hard masks or dry etching. The resulting devices had a channel length of 55 nm, achieved an on-current of 2.6×10^–6 A/µm at a drain bias (VD) of 40 mV, approximately four times higher than the TGTC and forty times higher than the TGBC which both had similar channel dimensions. At VD = 400 mV, a lateral field of 667 kV/cm, the on-current further increased to 1.6×10^–5 A/µm with the off-state current remaining in the 10^-13 A/µm range, giving an on/off ratio of 108. These results demonstrate that angled deposition provides both a nanolithography-free route to nanoscale patterning and a device architecture for integrating a-IGZO transistors into future nanoscale logic and memory technologies.